The title of the video is blunt: “30x Faster Than GPUs: Unveiling Cerebras CS-4 & WSE-3 Turbo.” The film itself, a five-minute narrated product tour uploaded to Cerebras's YouTube channel on September 3, 2026, is calmer. It never says 30x. It says the CS-4 runs frontier and open-source models “an order of magnitude faster than GPU solutions,” and then spends most of its time on something less glamorous: how the machine is powered, cooled, assembled and installed.

Cerebras unveiled the CS-4 on August 18, 2026 at its Supernova event, according to its launch announcement and The Next Web. It is the company's first system to put three of its wafer-scale processors in one rack. This article walks through what the film says, what Cerebras's product page adds, and what independent reporting makes of the claims, including the gap between “an order of magnitude” and “30x.”

Two parts: a power rack and a backpack

The narration says the CS-4 was designed around two principles: extract more performance from the wafer, and make the system easier to build, deploy and scale. It is made of two modular components. The first is the power rack. “Instead of an inert metal skeleton,” the film says, the rack supplies power and delivers cooling water. It takes in alternating current at up to 480 volts, and each backpack is fed by up to 30 power supplies that convert it to 54.5 volts of direct current. The supplies are hot-swappable, so maintenance does not take compute offline, and the rack can be installed before any compute arrives.

The second component is the backpack. Three of them attach to the rack, and each holds one wafer-scale engine along with the power, cooling and input-output hardware it needs. The film presents this as the main simplification: deploying a supercomputer becomes a matter of attaching a backpack to the rack. Once a backpack slides into place, power, cooling water and data connect automatically, “bringing a complete CS-4 online in minutes instead of days.” Cerebras's product page words the same benefit differently, saying the backpack cuts deployment time “from days to hours,” so the two claims are not identical.

Inside the backpack

Rather than a flat board, the film says, the backpack layers its parts vertically in a three-dimensional stack. Behind the wafer, a copper cold plate carries cooling water through channels. In front of it sits a compact power converter that feeds energy straight into the silicon. The film then offers its sharpest comparison. On a conventional GPU board the electrical path from power converter to processor is about 50 millimeters; on the CS-4 it is half a millimeter, which the narration says is “virtually eliminating power loss.” That arrangement, the film says, doubles the power delivered to the wafer, allowing higher operating frequencies and faster token generation. The product page says the packaging has half as many components as before, and the film closes on the line “Up to two times the performance, half the components.”

The short power path is more than a neat detail. A processor runs at a very low voltage, so it draws enormous current, and the power lost in a conductor grows with the square of that current. Every millimeter the current has to travel at that voltage wastes energy and adds heat. Shrinking the final stretch from about 50 millimeters to half a millimeter, a hundred times shorter, is a plausible route to both lower losses and the extra power the faster clock needs. That explanation is general engineering, not a measurement from Cerebras, which has not published the efficiency gain from this change alone.

The chip: WSE-3 Turbo

Most processors are cut from a silicon wafer into many small dies. Cerebras keeps the whole wafer as a single chip, about 46,225 square millimeters according to The Register, which is why it can put so many cores and so much memory on one piece of silicon. At the center of every backpack is the processor the film calls the world's largest computer chip. According to the video description and product page, each WSE-3 Turbo wafer has 4 trillion transistors and 900,000 AI cores, delivers 250 petaflops of compute and has 43.2 petabytes per second of memory bandwidth. Every core has its own memory beside its logic, and the cores are linked by nanoscale wires “instead of the thousands of cables needed on GPU systems.” The page sums up the upgrade as “Twice the compute. Twice the bandwidth. Less than half the latency.”

For the full rack, three wafers add up to 750 petaflops and 129.6 petabytes per second, according to The Next Web. Wafer-to-wafer latency is about two microseconds, cut from about five, and wafers connect within and across racks without a switch. Cerebras says the design supports models above 50 trillion parameters; The Register adds that it knows of no such model today. The video description says “sub-2 microsecond” latency while the product page says 2 microseconds, a small inconsistency in Cerebras's own wording.

What changed, and what did not

Independent coverage is clear that the silicon is the same. The Next Web notes that the WSE-3 Turbo carries the same four trillion transistors, the same 900,000 cores, the same 44 GB of on-chip SRAM and the same TSMC 5-nanometer process as the WSE-3 it replaces. The Register reaches the same reading, estimating that the clock roughly doubled, from about 1.4 to about 2.8 gigahertz, and that the wafer's power rose from about 15 kilowatts to an estimated 33. Both note that compute and bandwidth doubled almost exactly, which is what a faster clock would produce. The Register adds that the “Turbo” name likely reflects a quick respin. The Next Web reports a genuinely new design slated for 2027, and The Register expects that successor to roughly double the SRAM.

One consequence follows from the Sean Lie video covered separately on Lens. Because each wafer still holds 44 GB, the number of wafers needed to hold a given model does not shrink with the CS-4. A model that took 59 wafers in his whiteboard example still takes 59. What changes is how fast those wafers run, and how they are packaged: three to a rack, so that example would come to about 20 CS-4 systems (our arithmetic). The Register put it plainly: Cerebras “opted to double performance this generation rather than boost SRAM capacity.”

Taking apart “30x”

The headline number deserves the most scrutiny. According to The Next Web, the 30x figure is measured as per-user token speed, not system throughput, using one model, gpt-oss-120b, against unnamed GPU systems. The Register's article does not use the number. Its own arithmetic runs from Cerebras's claim of up to 4,400 tokens per second per user on a single CS-4 for that model, against about 350 tokens per second on the fastest GPU-based service tracked by Artificial Analysis. That works out to roughly 12.6 times, not 30.

So three figures are in circulation. The film says an order of magnitude. A published-numbers calculation by The Register gives about 12.6. The headline says up to 30. They are not necessarily in conflict: “up to” signals a best case, and the baselines differ. Cerebras's product page says the comparisons rely on third-party benchmarking or internal testing and that results “may vary depending on workload, configuration.” It does not name the GPU, the model or the workload behind the headline. A fair reading is that the CS-4 is much faster per user on one popular model against current GPU services, and that the exact multiple depends on a baseline the company has not published.

Per-user speed is also only one axis. A system can be fast for one person and still expensive per token if it serves few people at once. Cerebras's own companion post on large-model deployment says the more meaningful metric is total token throughput per unit of power, measured at the same output speed. A like-for-like comparison would fix the model, the numerical precision, the context length and the output speed, and then compare tokens per second per kilowatt and per dollar. None of those figures has been published for the CS-4 against a named GPU system.

Peak numbers and power

The compute figure carries its own asterisk. The 250 petaflops per wafer is a sparse FP16 number; both The Next Web and The Register put the dense figure at 25 petaflops, about a tenth. The Register notes that sparsity generally does not help language-model inference and that the latest AMD and Nvidia GPUs offer roughly 4 to 5 petaflops of dense FP16 compute. It also suspects the peak memory bandwidth is theoretical, since the previous chip lacked the compute to saturate its SRAM during inference. That is a reason to treat the 43.2 petabytes per second as a ceiling, not a measurement.

On power, Cerebras claims up to ten times the throughput per watt of the CS-3. It has not published rack power. The Register estimates a total system draw between 120 and 140 kilowatts, roughly half of comparable AMD and Nvidia rack systems expected later this year, while flagging that chip power, rack power and clock speed are all its own estimates and that one spec-table figure is ambiguous. Treat the efficiency claim as plausible but unverified until measured power and speed appear for the same workload.

A system built for decoding

The Register describes the CS-4 as pipeline-parallel: wafers are linked in a two-dimensional torus with direct chip-to-chip connections and no switches, and the chips work primarily as decode accelerators. Prompt processing, which needs large amounts of raw compute, is offloaded to other hardware, with AWS Trainium and AMD Instinct named as partners. The CS-4 is also described as the first system built on what Cerebras calls its Nexus platform architecture, which splits the design into three elements: compute, power and input-output. The Register adds that switched Ethernet is also supported for larger deployments, but “the compromise is your latencies may be a bit higher,” which is why the direct links matter for models split across many wafers. Switchless links are a deliberate contrast with designs such as AWS's Trainium3, which uses a switched fabric. For an operator, that is the film's real argument: the machine is meant to be quick to deploy, easy to service and ready for later generations of wafers.

Customers, price and timing

The product page says first CS-4 shipments begin “this quarter” without a date, and The Next Web reports that first units were expected before the quarter ended. Cerebras disclosed no CS-4 customer agreements and no pricing at launch, and no volumes or delivery schedule. The partners named alongside the launch, including OpenAI, G42, MBZUAI and AWS, are not confirmed buyers of this system. A banner on Cerebras's site says Oracle Cloud Infrastructure plans to offer Cerebras inference to AI labs, enterprises and developers, though it does not say that offering runs on the CS-4.

What to watch next

  • Independent benchmarks across several models, with the GPU baselines named.
  • Measured power at the rack, for the same workloads as the speed claims.
  • The first named CS-4 customers and the price of a system.
  • Whether the claimed 50-trillion-parameter reach is ever exercised by a real model.
  • The 2027 generation, which independent reporting says must come from new silicon rather than a faster clock.

The film makes a clear case that the CS-4 is simpler to install and run than what came before, and the engineering behind that case, from the short power path to the hot-swappable supplies, is concrete. The headline number is where its marketing outruns its evidence. Readers should hold the speed claim until someone outside the company publishes the test, with the model, the precision and the GPU baseline all named.

Sources and notes

Video: 30x Faster Than GPUs: Unveiling Cerebras CS-4 & WSE-3 Turbo, Cerebras, September 3, 2026 (5:10). Product page: Cerebras CS-4. Coverage: The Next Web, The Register. Related: Cerebras CTO Sean Lie on serving trillion-parameter models. Thumbnail: still from the video, Cerebras.